HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 351

IC H8 MCU FLASH 128K 100-QFP

HD64F3067RF20

Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3067RF20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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9.1
The H8/3067 Group has built-in 16-bit timer module with three 16-bit counter channels.
9.1.1
16-bit timer features are listed below.
Capability to process up to 6 pulse outputs or 6 pulse inputs
Six general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
Selection of eight counter clock sources for each channel:
Internal clocks: , /2, /4, /8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
Five operating modes selectable in all channels:
Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
High-speed access via internal 16-bit bus
The TCNTs and GRs can be accessed at high speed via a 16-bit bus.
Any initial timer output value can be set
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
Input capture function
Rising edge, falling edge, or both edges (selectable)
Counter clearing function
Counters can be cleared by compare match or input capture
Synchronization
Two or more timer counters (TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
three-phase PWM output is possible
Features
Overview
Section 9 16-Bit Timer
Rev. 4.00 Jan 26, 2006 page 327 of 938
Section 9 16-Bit Timer
REJ09B0276-0400

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