DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 351
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 351 of 980
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Bit
3
2
Bit Name
TGFD
TGFC
Initial
value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag D
R/(W)* Input Capture/Output Compare Flag C
Description
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0 and 3. Only 0 can
be written, for flag clearing. In channels 1, 2, 4, and 5, bit 3
is reserved. It is always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3. Only 0 can
be written, for flag clearing. In channels 1, 2, 4, and 5, bit 2
is reserved. It is always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRD and TGRD is functioning as
output compare register
When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
When DTC is activated by TGID interrupt, the DISEL bit
of MRB in DTC is 0 with the transfer counter other than
0
When 0 is written to TGFD after reading TGFD = 1
When TCNT = TGRC and TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
When DTC is activated by TGIC interrupt, the DISEL bit
of MRB in DTC is 0 with the transfer counter other than
0
When 0 is written to TGFC after reading TGFC = 1
Rev. 6.00 Sep. 24, 2009 Page 303 of 928
Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0099-0600
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