UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 249

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2-L
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
Caution
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(B) → (E)
(C) → (F)
(D) → (G)
Status Transition
(D) → (C) (X1 clock)
(D) → (C) (external main system clock)
(B) → (H)
(C) → (I)
Note 78K0/KC2-L only
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Note 78K0/KC2-L only
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
Note
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figures 5-18 and 5-19.
been set.
(Setting sequence of SFR registers)
Note
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
When transitioning to the STOP mode, it is possible to achieve low power consumption by setting RMC = 56H
first.
Setting Flag of SFR Register
2. EXCLK, OSCSEL:
Status Transition
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (4/4)
(Setting sequence)
Unnecessary if these
registers are already
EXCLK
0
1
Bits 7 and 6 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
set
OSCSEL
1
1
the high-speed system
CPU is operating with
MSTOP
Unnecessary if the
0
0
clock
Must not be
Register
checked
Must be
checked
OSTC
Setting
Setting
Note
CHAPTER 5 CLOCK GENERATOR
Executing STOP instruction
register is already set
XSEL
Unnecessary if this
Note
1
1
Note
MCM0
1
1
CSS
0
0
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