UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 251
UPD78F0552MA-FAA-AX
Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0552MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 251 of 822
- Download datasheet (6Mb)
78K0/Kx2-L
5.6.8 Time required for switchover of CPU clock and main system clock
be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can
be changed.
switchover clock for several clocks (refer to Tables 5-8 and 5-9).
of the PCC register.
Table 5-8. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor (78K0/KY2-L,
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
CSS PCC2 PCC1 PCC0
Set Value Before
PCC2
0
1
Set Value Before
0
0
0
0
1
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the pre-
Whether the CPU is operating on the main system clock or the subsystem clock
Note 78K0/KC2-L only
Remark The number of clocks listed in Table 5-8 is the number of CPU clocks before switchover.
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
Remark 1. The number of clocks listed in Table 5-9 is the number of CPU clocks before switchover.
Switchover
Switchover
0
0
0
0
1
×
Table 5-9. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
PCC1
0
0
1
1
0
0
0
1
1
0
×
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing
CSS from 1 to 0).
0
1
0
1
0
×
PCC0
0
1
0
1
0
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
PCC2
8 clocks
4 clocks
2 clocks
2 clocks
1 clock
0
0
8 clocks
4 clocks
2 clocks
1 clock
0
PCC1
0
0
PCC0
0
0
16 clocks
4 clocks
2 clocks
2 clocks
1 clock
0
PCC2
0
0
16 clocks
78K0/KA2-L, and 78K0/KB2-L)
4 clocks
2 clocks
1 clock
PCC1
1
0
0
PCC0
(78K0/KC2-L)
1
16 clocks
2 clocks
Set Value After Switchover
8 clocks
2 clocks
1 clock
0
Set Value After Switchover
PCC2
1
0
16 clocks
0
8 clocks
2 clocks
1 clock
PCC1
1
0
16 clocks
8 clocks
4 clocks
2 clocks
1 clock
PCC0
0
0
1
PCC2
CHAPTER 5 CLOCK GENERATOR
0
1
Note
16 clocks
8 clocks
4 clocks
1 clock
can be ascertained using bit 5 (CLS)
0
PCC1
1
16 clocks
8 clocks
4 clocks
2 clocks
2 clocks
1
PCC0
1
0
0
PCC2
1
f
1
f
f
f
XP
16 clocks
f
XP
XP
XP
8 clocks
4 clocks
2 clocks
XP
/16f
/2f
/4f
/8f
/f
PCC1
SUB
×
0
SUB
SUB
SUB
SUB
clocks
clocks
clocks
clocks
×
clocks
PCC0
0
×
237
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