UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 669

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
generated.
voltage detection, and each item of hardware is set to the status shown in Tables 20-1 and 20-2. Each pin is high
impedance during reset signal generation or during the oscillation stabilization time just after a reset release.
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-
speed oscillation clock (refer to Figures 20-2 to 20-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when V
internal high-speed oscillation clock (refer to CHAPTER 21 POWER-ON-CLEAR CIRCUIT and CHAPTER 22 LOW-
VOLTAGE DETECTOR) after reset processing.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The reset function is mounted onto all 78K0/Kx2-L microcontroller products.
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage from external input
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
Cautions 1. For an external reset, input a low level for 10
Note 78K0/KC2-L only
pin (EXLVI pin), and detection voltage
2. During reset signal generation, the X1 clock, XT1 clock
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held during
(If an external reset is effected upon power application, the period during which the supply
voltage is outside the operating range (V
level input may be continued before POC is released.)
and internal low-speed oscillation clock stop oscillating. External main system clock input and
external subsystem clock
reset input. However, because SFR is initialized, the port pins become high-impedance.
CHAPTER 20 RESET FUNCTION
DD
Note
≥ V
input become invalid.
POR
or V
DD
≥ V
DD
< 1.8 V) is not counted in the 10
LVI
μ
s or more to the RESET pin.
after the reset, and program execution starts using the
Note
, internal high-speed oscillation clock,
CHAPTER 20 RESET FUNCTION
μ
s. However, the low-
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