UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 517

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(5) IICA low-level width setting register (IICWL)
(6) IICA high-level width setting register (IICWH)
(7) Port input mode register 6 (PIM6)
This register sets the input buffer of P60 and P61 in 1-bit units. When using an input compliant with the SMBus
specifications in I
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA being in
master mode.
This register can be set by an 8-bit memory manipulation instruction.
Set this register while operation of I
Reset signal generation sets this register to FFH.
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA being
in master mode.
This register can be set by an 8-bit memory manipulation instruction.
Set this register while operation of I
Reset signal generation sets this register to FFH.
Remark
Address: FF3EH
Symbol
PIM6
For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting transfer
clock by using IICWL and IICWH registers.
2
PIM6n
C communication, set PIM60 and PIM61 to 1.
Figure 15-10. Format of IICA High-Level Width Setting Register (IICWH)
Address: FFADH
Address: FFAEH
Figure 15-9. Format of IICA Low-Level Width Setting Register (IICWL)
7
0
0
1
After reset: 00H
Symbol
Symbol
IICWH
IICWL
Figure 15-11. Format of Port Input Mode Register 6 (PIM6)
Normal input (Schmitt) buffer
SMBus input buffer
6
0
7
7
2
2
C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0).
C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0).
R/W
After reset: FFH R/W
After reset: FFH R/W
6
6
5
0
5
5
P6n pin input buffer selection (n = 0, 1)
4
0
4
4
3
3
3
0
CHAPTER 15 SERIAL INTERFACE IICA
2
2
2
0
1
1
0
0
PIM61
1
PIM60
0
503