UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 119

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
FFECH to
FFEFH
FFBAH
FFBBH
FFBCH
FFBDH
FFBEH
FFBFH
FFC0H to
FFDFH
FFE0H
FFE1H
FFE2H
FFE3H
FFE4H
FFE5H
FFE6H
FFE7H
FFE8H
FFE9H
FFEAH
FFEBH
FFF0H
FFF1H to
FFFAH
Address
FFFBH
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1. The reset values of LVIM vary depending on the reset source and setting of option byte.
Remark
TMC00
PRM00
CRC00
TOC00
LVIM
LVIS
IF0
IF1
MK0
MK1
PR0
PR1
IMS
PCC
Symbol
2. The reset values of LVIS vary depending on the reset source.
3. 48-pin products only.
4. 44-pin and 48-pin products only.
5. Reset signal generation makes the setting of the ROM area undefined.
−
−
−
IF0L
IF0H
IF1L
IF1H
MK0L
MK0H
MK1L
MK1H
PR0L
PR0H
PR1L
PR1H
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
corresponding to each product as indicated in Table 3-1 after release of reset.
<TMIF010> <TMIF000> <TMIF50> <TMIFH0> <TMIFH1> <CSIIF10>
<LVION>
<PMK8>
<SREIF6> <PIF5> <PIF4> <PIF3> <PIF2> <PIF1> <PIF0> <LVIIF>
<PIF8>
<SREMK6>
<TMMK
<TMPR
<PPR8>
<SREPR6>
ES110 ES100 ES010
RAM2
010>
010>
Note4
Note4
Note4
7
0
0
0
0
−
0
1
1
−
−
0
<OSPT00> <OSPE00> TOC004
<PMK5> <PMK4> <PMK3> <PMK2> <PMK1> <PMK0> <LVIMK>
<TMMK
<PMK7>
<TMPR
<PPR7>
<PIF7>
<PPR5> <PPR4> <PPR3> <PPR2> <PPR1> <PPR0> <LVIPR>
XTSTA
RAM1
000>
000>
Note3
Note3
Note3
RT
−
−
−
6
0
0
0
0
0
1
1
Table 3-10. Special Function Register List: 78K0/KC2-L (6/6)
<RTCM
<TMMK
<RTCP
<CLS> <CSS>
<RTCI
RAM0
<TMP
R50>
50>
R>
F>
K>
−
−
−
5
0
0
0
0
0
1
1
<KRIF>
<KRMK>
<KRPR>
<PIF11> <PIF10> <PIF9>
<TMMK
<PMK1
ES000
<TMP
<PPR
RH0>
H0>
11>
1>
4
0
0
−
−
0
−
0
0
Bit No.
<LVS00> <LVR00>
TMC003 TMC002 TMC001 <OVF00>
<TMMK
<PMK1
<TMMK
<TMPR
<TMIF
ROM3
LVIS3
<TMP
RH1>
<PPR
H1>
10>
51>
51>
51>
0>
−
−
−
3
0
0
0
0
<LVISEL>
<CSIPR
<RTCIP
<PPR9>
CRC002 CRC001 CRC000
<RTCII
<PMK9
<CSIM
<RTCI
ROM2
LVIS2
PCC2
MK>
K10
10>
R>
F>
−
−
−
2
0
>
<LVIMD> <LVIF>
<STIF6> <SRIF6>
<PPR6>
PRM001 PRM000
TOC001
<PIF6>
<PMK6>
<STPR
<CSIIF
<STMK
ROM1
LVIS1
<CSIM
<CSIP
PCC1
R11>
K11>
11>
Note3
Note3
Note3
6>
6>
1
−
−
−
<TOE00>
<ADIF>
<ADMK>
<ADPR>
<SRMK
<IICAM
<SRPR
<IICAP
<IICAI
ROM0
LVIS0
PCC0
R0>
F0>
K0>
6>
6>
0
−
−
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
CHAPTER 3 CPU ARCHITECTURE
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
1
√
√
√
√
Simultaneously
Number of Bits
Manipulated
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
8
√
√
√
√
Therefore, set the value
16
−
−
−
−
−
−
−
√
√
√
√
√
√
−
−
−
−
CFH
00H
Reset
After
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
01H
Note1
−
−
−
Note2
Note5
248
253
249
251
672
675
598
598
598
598
606
606
606
606
613
613
613
613
699
204
−
−
−
105