UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 515

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(4) IICA control register 1 (IICACTL1)
Address: FFA8H
IICACTL1
Symbol
This register is used to set the operation mode of I
This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are
read-only.
Set the IICACTL1 register, except the WUP bit, while operation of I
register 0 (IICACTL0) is 0).
Reset signal generation clears this register to 00H.
Notes 1.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) WUP
bit (see Figure 15-23 Flow When Setting WUP = 1).
Clear (0) the WUP bit after the address has matched or an extension code has been received. The subsequent
communication can be entered by clearing (0) the WUP bit (The wait must be released and transmit data must
be written after the WUP bit has been cleared (0).).
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to 1.
Condition for clearing (WUP = 0)
• Cleared by instruction (after address match or
extension code reception)
WUP
WUP
7
0
1
2.
SDAA0
SCLA0
After reset: 00H
Bits 4 and 5 are read-only.
The status of IICAS0 must be checked and WUP must be set during the period shown below.
Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (1/2)
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
6
0
Check the IICAS0 operation status and set
WUP during this period.
CLD0
<5>
R/W
Note 1
<1>
DAD0
<4>
The maximum time from reading IICAS0 to setting
WUP is the period from <1> to <2>.
2
Control of address match wakeup
C and detect the statuses of the SCLA0 and SDAA0 pins.
A6
SMC0
<3>
A5
Condition for setting (WUP = 1)
• Set by instruction (when MSTS0, EXC0, and COI0
are “0”, and STD0 also “0” (communication not
entered))
A4
2
CHAPTER 15 SERIAL INTERFACE IICA
C is disabled (bit 7 (IICE0) of IICA control
DFC0
<2>
Note 2
A3
A2
1
0
A1
A0
0
0
<2>
R/W
501