UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 8

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 118
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 198
3.4 Operand Address Addressing .................................................................................................. 109
4.1 Port Functions ............................................................................................................................ 118
4.2 Port Configuration...................................................................................................................... 125
4.3 Registers Controlling Port Function ........................................................................................ 167
4.4 Port Function Operations .......................................................................................................... 185
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 186
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 197
5.1 Functions of Clock Generator................................................................................................... 198
5.2 Configuration of Clock Generator ............................................................................................ 199
5.3 Registers Controlling Clock Generator.................................................................................... 202
5.4 System Clock Oscillator ............................................................................................................ 213
5.5 Clock Generator Operation ....................................................................................................... 217
5.6 Controlling Clock........................................................................................................................ 220
3.3.1 Relative addressing....................................................................................................................... 106
3.3.2 Immediate addressing ................................................................................................................... 107
3.3.3 Table indirect addressing .............................................................................................................. 108
3.3.4 Register addressing ...................................................................................................................... 109
3.4.1 Implied addressing ........................................................................................................................ 109
3.4.2 Register addressing ...................................................................................................................... 110
3.4.3 Direct addressing .......................................................................................................................... 111
3.4.4 Short direct addressing ................................................................................................................. 112
3.4.5 Special function register (SFR) addressing ................................................................................... 113
3.4.6 Register indirect addressing.......................................................................................................... 114
3.4.7 Based addressing.......................................................................................................................... 115
3.4.8 Based indexed addressing ............................................................................................................ 116
3.4.9 Stack addressing........................................................................................................................... 117
4.2.1 Port 0............................................................................................................................................. 126
4.2.2 Port 1............................................................................................................................................. 129
4.2.3 Port 2............................................................................................................................................. 141
4.2.4 Port 3............................................................................................................................................. 147
4.2.5 Port 4............................................................................................................................................. 152
4.2.6 Port 6............................................................................................................................................. 155
4.2.7 Port 7............................................................................................................................................. 160
4.2.8 Port 12........................................................................................................................................... 162
4.4.1 Writing to I/O port .......................................................................................................................... 185
4.4.2 Reading from I/O port.................................................................................................................... 185
4.4.3 Operations on I/O port................................................................................................................... 185
5.4.1 X1 oscillator................................................................................................................................... 213
5.4.2 XT1 oscillator ................................................................................................................................ 213
5.4.3 When subsystem clock is not used ............................................................................................... 216
5.4.4 Internal high-speed oscillator ........................................................................................................ 216
5.4.5 Internal low-speed oscillator.......................................................................................................... 216
5.4.6 Prescaler ....................................................................................................................................... 216
5.6.1 Example of controlling high-speed system clock ........................................................................... 220
5.6.2 Example of controlling internal high-speed oscillation clock.......................................................... 223