UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 414

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
11.4 Operations of Clock Output Controller
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(2) Port mode register 4 (PM4)
The clock pulse is output as the following procedure.
<1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register
<2> Set bit 4 (CLOE) of CKS to 1 to enable clock output.
Remark
Remarks 1. f
This register sets port 4 input/output in 1-bit units.
When using the P42/PCL/SSI11/INTP6 pin for clock output, clear PM42 and the output latches of P42 to 0.
PM4 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM4 to FFH.
(CKS) (clock pulse output in disabled status).
Clock output
The clock output controller is designed not to output pulses with a small width during output enable/disable
switching of the clock output. As shown in Figure 11-4, be sure to start output from the low period of the
clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock.
Remark
2. f
CLOE
Address: FF24H
Symbol
PM4
PRS
SUB
: Peripheral hardware clock frequency
: Subsystem clock frequency
The figure shown above presents the format of port mode register 4 of 48-pin products
(78K0/KC2-L).
PM4n
Figure 11-4. Remote Control Output Application Example
*
7
1
0
1
Figure 11-3. Format of Port Mode Register 4 (PM4)
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
6
1
5
1
P4n pin I/O mode selection (n = 0 to 2)
R/W
4
1
CHAPTER 11 CLOCK OUTPUT CONTROLLER
3
1
*
PM42
2
PM41
1
PM40
0
400