AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 16

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Data output
Write Data Hold Time
During write cycles in both protocols, output data becomes
valid after the falling edge of the NWE signal and remains
valid after the rising edge of NWE, as illustrated in the fig-
ure below. The external NWE waveform (on the NWE pin)
is used to control the output data timing to guarantee this
operation.
It is therefore necessary to avoid excessive loading of the
NWE pins, which could delay the write signal too long and
cause a contention with a subsequent read cycle in stan-
dard protocol.
Figure 16. Data Hold Time
In early read protocol the data can remain valid longer than
in standard read protocol due to the additional wait cycle
which follows a write access.
16
ADDR
MCKI
NWE
AT91M63200
Wait States
The EBI can automatically insert wait states. The different
types of wait states are listed below:
•
•
•
•
•
Standard Wait States
Each chip select can be programmed to insert one or more
wait states during an access on the corresponding device.
This is done by setting the WSE field in the corresponding
EBI_CSR. The number of cycles to insert is programmed in
the NWS field in the same register.
Below is the correspondence between the number of stan-
dard wait states programmed and the number of cycles
during which the NWE pulse is held low:
For each additional wait state programmed, an additional
cycle is added.
Figure 17. One Wait State Access
Notes:
ADDR
Standard wait states
Data float wait states
External wait states
Chip select change wait states
Early read wait states (as described in “Read Protocols”)
MCKI
NWE
NRD
NCS
0 wait states
1 wait state
1. Early read protocol
2. Standard read protocol
(1)
1 wait state access
(2)
1/2 cycle
1 cycle