AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 85
![IC ARM7 MCU 176 TQFP](/photos/12/32/123243/313-176-lqfp_sml.jpg)
AT91M63200-25AI
Manufacturer Part Number
AT91M63200-25AI
Description
IC ARM7 MCU 176 TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91M43300-25CI.pdf
(21 pages)
2.AT91M43300-25CI.pdf
(5 pages)
3.AT91M63200-25AI.pdf
(12 pages)
4.AT91M63200-25AI.pdf
(153 pages)
Specifications of AT91M63200-25AI
Core Processor
ARM7
Core Size
16/32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-TQFP, 176-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
USART Interrupt Mask Register
Name:
Access Type:
•
•
•
•
•
•
•
•
•
•
•
•
RXRDY: RXRDY Interrupt Mask
0 = RXRDY Interrupt is disabled.
1 = RXRDY Interrupt is enabled.
TXRDY: TXRDY Interrupt Mask
0 = TXRDY Interrupt is disabled.
1 = TXRDY Interrupt is enabled.
RXBRK: Receiver Break Interrupt Mask
0 = Receiver Break Interrupt is disabled.
1 = Receiver Break Interrupt is enabled.
ENDRX: End of Receive Transfer Interrupt Mask
0 = End of Receive Transfer Interrupt is disabled.
1 = End of Receive Transfer Interrupt is enabled.
ENDTX: End of Transmit Transfer Interrupt Mask
0 = End of Transmit Transfer Interrupt is disabled.
1 = End of Transmit Transfer Interrupt is enabled.
OVRE: Overrun Error Interrupt Mask
0 = Overrun Error Interrupt is disabled.
1 = Overrun Error Interrupt is enabled.
FRAME: Framing Error Interrupt Mask
0 = Framing Error Interrupt is disabled.
1 = Framing Error Interrupt is enabled.
PARE: Parity Error Interrupt Mask
0 = Parity Error Interrupt is disabled.
1 = Parity Error Interrupt is enabled.
TIMEOUT: Time-out Interrupt Mask
0 = Receive Time-out Interrupt is disabled.
1 = Receive Time-out Interrupt is enabled.
TXEMPTY: TXEMPTY Interrupt Mask
0 = TXEMPTY Interrupt is disabled.
1 = TXEMPTY Interrupt is enabled.
COMMTX: ARM7TDMI ICE Debug Communication Channel Transmit Interrupt Mask
This bit is implemented for USART0 only.
0 = COMMTX Interrupt is disabled.
1 = COMMTX Interrupt is enabled.
COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Interrupt Mask
This bit is implemented for USART0 only.
0 = COMMRX Interrupt is disabled.
1 = COMMRX Interrupt is enabled.
COMMRX
PARE
31
23
15
–
–
7
COMMTX
FRAME
30
22
14
US_IMR
Read only
–
–
6
OVRE
29
21
13
–
–
–
5
ENDTX
28
20
12
–
–
–
4
ENDRX
27
19
11
–
–
–
3
RXBRK
26
18
10
–
–
–
2
AT91M63200
TXEMPTY
TXRDY
25
17
–
–
9
1
TIMEOUT
RXRDY
24
16
–
–
8
0
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