AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 73

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Baud Rate Generator
The Baud Rate Generator provides the bit period clock (the
baud rate clock) to both the receiver and the transmitter.
The Baud Rate Generator can select between external and
internal clock sources. The external clock source is SCK.
The internal clock sources can be either the master clock
MCKI or the master clock divided by 8 (MCKI/8).
Note: In all cases, if an external clock is used, the duration
of each of its levels must be longer than the system clock
(MCKI) period. The external clock frequency must be at
least 2.5 times lower than the system clock.
When the USART is programmed to operate in asynchro-
nous mode (SYNC = 0 in the Mode Register US_MR), the
selected clock is divided by 16 times the value (CD) written
i n US _ B R G R ( B a u d Ra t e G e ne r at o r R eg i s t e r ) . I f
US_BRGR is set to 0, the baud rate clock is disabled.
Figure 40. Baud Rate Generator
MCKI/8
MCKI
Baud Rate
SCK
USCLKS [0]
=
0
1
Selected Clock
USCLKS [1]
16 x CD
0
1
CLK
16-bit Counter
CD
USCLKS [1]
SYNC
OUT
0
When the USART is programmed to operate in synchro-
nous mode (SYNC = 1) and the selected clock is internal
(USCLKS[1] = 0 in the Mode Register US_MR), the baud
rate clock is the internal selected clock divided by the value
written in US_BRGR. If US_BRGR is set to 0, the baud rate
clock is disabled.
In synchronous mode with external clock selected
(USCLKS[1] = 1), the clock is provided directly by the sig-
nal on the SCK pin. No division is active. The value written
in US_BRGR has no effect.
CD
>1
1
0
Baud Rate
0
1
=
Selected Clock
AT91M63200
CD
Divide
by 16
SYNC
0
1
Baud Rate
Clock
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