UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 130

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

I
23.9
23.9.1
130/300
2
C interface
Table 77.
1. These values are beyond the bit rate supported by UPSD34xx.
I
The S1STA register provides status regarding immediate activity and the current state of
operation on the I
the interrupt flag.
Interrupt conditions
If the I
and the SIOE is initialized, then an interrupt is automatically generated when any one of the
following five events occur:
●
●
●
●
●
Selected Slave mode means the device address sent by the Master device at the beginning
of the current data transfer matched the address stored in the S1ADR register.
If the I
Table 78.
2
C interface status register (S1STA)
Bit 7
CR2
GC
When the SIOE receives an address that matches the contents of the SFR, S1ADR.
Requirements: SIOE is in Slave Mode, and bit AA = 1 in the SFR S1CON.
When the SIOE receives General Call address. Requirments: SIOE is in Slave Mode,
bit AA = 1 in the SFR S1CON
When a complete data byte has been received or transmitted by the SIOE while in
Master mode. The interrupt will occur even if the Master looses arbitration.
When a complete data byte has been received or transmitted by the SIOE while in
selected Slave mode.
A Stop condition on the bus has been recognized by the SIOE while in selected Slave
mode.
0
0
0
0
1
1
1
1
2
2
C interrupt is enabled (EI
C interrupt is not enabled, the MCU may poll the INTR flag in S1STA.
Selection of the SCL frequency in Master mode based on f
S1STA: I
STOP
Bit 6
CR1
0
0
1
1
0
0
1
1
2
C bus. All bits in this register are read-only except bit 5, INTR, which is
2
C interface status register (SFR DDh, reset value 00h)
INTR
Bit 5
CR0
0
1
0
1
0
1
0
1
2
C = 1 in SFR named IEA, and EA =1 in SFR named IE),
TX_MODE
Bit 4
divided
1920
f
120
240
480
960
by:
OSC
32
48
60
UPSD3422, UPSD3433, UPSD3434, UPSD3454
BBUSY
Bit 3
12 MHz
f
12.5
6.25
375
250
200
100
OSC
50
25
BLOST
Bitrate (kHz) @ f
Bit 2
24 MHz
f
12.5
750
500
400
200
100
OSC
50
25
ACK_RESP
36 MHz
Bit 1
18.75
f
37.5
X
750
600
300
150
OSC
75
(1)
OSC
OSC
examples
40 MHz
Bit 0
f
SLV
X
833
666
333
166
OSC
20
83
41
(1)