UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 20

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

Description
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Description
The Turbo Plus UPSD34xx Series combines a powerful 8051-based microcontroller with a
flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal
embedded controller. At its core is a fast 4-cycle 8032 MCU with a 4-byte instruction
prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC). The MCU is
connected to a 16-bit internal instruction path to maximize performance, enabling loops of
code in smaller localities to execute extremely fast. The 16-bit wide instruction path in the
Turbo Plus Series allows double-byte instructions to be fetched from memory in a single
memory cycle. This keeps the average performance near its peak performance (peak
performance for 5 V, 40 MHz Turbo Plus UPSD34xx is 10 MIPS for single-byte instructions,
and average performance will be approximately 9 MIPS for mix of single- and multi-byte
instructions).
USB 2.0 (full speed, 12Mbps) is included, providing 10 endpoints, each with its own 64-byte
FIFO to maintain high data throughput. Endpoint 0 (control endpoint) uses two of the 10
endpoints for In and Out directions, the remaining eight endpoints may be allocated in any
mix to either type of transfers: Bulk or Interrupt.
Code development is easily managed without a hardware in-circuit emulator by using the
serial JTAG debug interface. JTAG is also used for in-system programming (ISP) in as little
as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to
programmable system device (PSD) architecture to optimize the 8032 memory structure,
offering two independent banks of Flash memory that can be placed at virtually any address
within 8032 program or data address space, and easily paged beyond 64 Kbytes using on-
chip programmable decode logic.
Dual Flash memory banks provide a robust solution for remote product updates in the field
through in-application programming (IAP). Dual Flash banks also support EEPROM
emulation, eliminating the need for external EEPROM chips.
General-purpose programmable logic (PLD) is included to build an endless variety of glue-
logic, saving external logic devices. The PLD is configured using the software development
tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge.
The UPSD34xx also includes supervisor functions such as a programmable watchdog timer
and low-voltage reset.
For a list of known limitations of the UPSD34xx devices, please refer to
Important
notes.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Section 34: