UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 34

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

8032 MCU core performance enhancements
5.1
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Figure 7.
Pre-fetch queue (PFQ) and branch cache (BC)
The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture,
to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The
PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch
two bytes (word) of code from program memory during any idle bus periods. Only necessary
word will be fetched (no dummy fetches like standard 8032). The PFQ will queue up to four
code bytes in advance of execution, which significantly optimizes sequential program
performance. However, when program execution becomes non-sequential (program
branch), a typical pre-fetch queue will empty itself and reload new code, causing the MCU to
stall. The Turbo UPSD34xx diminishes this problem by using a Branch Cache with the PFQ.
The BC is a four-way, fully associative cache, meaning that when a program branch occurs,
its branch destination address is compared simultaneously with four recent previous branch
destinations stored in the BC. Each of the four cache entries contain up to four bytes of code
related to a branch. If there is a hit (a match), then all four code bytes of the matching
program branch are transferred immediately and simultaneously from the BC to the PFQ,
and execution on that branch continues with minimal delay. This greatly reduces the chance
that the MCU will stall from an empty PFQ, and improves performance in embedded control
systems where it is quite common to branch and loop in relatively small code localities.
By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the
PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON).
The memory in the PSD module operates with variable wait states depending on the value
specified in the SFR named BUSCON. For example, a 5 V UPSD34xx device operating at a
40 MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In
this example, once the PFQ has one word of code, the wait states become transparent and
a full 10 MIPS is achieved when the program stream consists of sequential one- or two-byte,
one machine-cycle instructions as shown in
machine-cycle is four MCU clocks which equals the memory pre-fetch wait time that is also
program
memory
on PSD
module
16-bit
Instruction pre-fetch queue and branch cache
Branch
Cache
Instruction byte
Instruction byte
(BC)
Address
Wait
Branch 4
code
Branch 3
16
8
8
code
Load on branch address match
Branch 2
code
Branch 4
Branch 1
4 bytes of instruction
code
code
Instruction pre-fetch queue (PFQ)
Branch 3
16
code
Branch 2
code
Branch 1
code
UPSD3422, UPSD3433, UPSD3434, UPSD3454
16
Figure 6 on page 33
Compare
Instruction byte
(transparent because a
Address
Wait
16
8
address
Current
branch
MCU
8032
AI10431b