UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 249

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

UPSD3422, UPSD3433, UPSD3434, UPSD3454
Note:
It is recommended to prevent unused inputs from floating on Ports A, B, C, and D by pulling
them up to V
register to “output” at run-time for all unused inputs. This will prevent the CMOS input buffers
of unused input pins from drawing excessive current.
The csiop PMMR register definitions are shown in
page
Table 200. Power management mode register PMMR0 (address = csiop + offset
1. All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not
2. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 201. Power management mode register PMMR2 (address = csiop + offset
Bit 0
Bit 1 APD Enable
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
clear the registers.
csiop PMMR registers. Current consumption of the PLDs is directly related to the
composite frequency of all transitions on PLD inputs, so blocking certain PLD inputs
can significantly lower PLD operating frequency and power consumption (resulting in a
lower frequency on the graphs of
250.
Blocking Bit,
Blocking Bit,
Blocking Bit,
PLD Turbo
CLKIN to
CLKIN to
PLDs
PLDs
Disable
Only
OMCs
WR to
X
X
X
X
X
X
DD
B0h)
B4h)
(2)
(2)
(2)
with a weak external resistor (100K
(1)
(1)
0 =
1 =
0 =
1 =
0 =
1 =
0 =
1 =
on
off
on
off
on
off
on
off
0
0
1
0
0
0
0
0
Not used, and should be set to zero.
Automatic Power Down (APD) counter is disabled.
APD counter is enabled
Not used, and should be set to zero.
PLD Turbo mode is on
PLD Turbo mode is off, saving power.
CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of
CLKIN powers-up the PLDs.
CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still
goes to APD counter.
CLKIN input is not blocked from reaching all OMCs’ common clock
inputs.
CLKIN input to common clock of all OMCs is blocked, saving power. But
CLKIN still goes to APD counter and all PLD logic besides the common
clock input on OMCs.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
8032 WR input to the PLD Input Bus is not blocked.
8032 WR input to PLD Input Bus is blocked, saving power.
Figure 95 on page 265
Table 200
Ω
), or by setting the csiop Direction
through
and
Figure 96 on page
Table 202 on
PSD module
249/300
266).