UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 193

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.1.4
28.1.5
28.1.6
28.1.7
Secondary Flash memory
The smaller Secondary Flash memory is also divided into equal sized sectors that are
individually selectable by the Decode PLD signals, named CSBOOTx, one signal for each
Secondary Flash memory sector. Each sector can be located at any address within 8032
program address space (accessed with PSEN) or XDATA space (accessed with RD or WR)
as defined with PSDsoft Express. The user only has to specify an address range for each
segment, and specify if Secondary Flash memory will reside in 8032 data or program
address space, and then PSEN, RD, or WR are automatically activated for the specified
range. 8032 firmware is easily programmed into Secondary Flash memory using PSDsoft
Express and others. See
SRAM
The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be
located at any address within 8032 XDATA space (accessed with RD or WR). These choices
are specified using PSDSoft Express, where the user specifies an SRAM address range.
See
Table 157. UPSD34xx memory configuration
Runtime control registers, csiop
A block of 256 bytes is decoded inside the PSD module for module control and status (see
Table 162 on page
sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal,
CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed
with RD and WR signals. The address range of csiop is specified using PSDsoft Express
where the user only has to specify an address range of 256 bytes, and then the RD or WR
signals are automatically activated for the specified range. Individual registers within this
block are accessed with an offset from the specified csiop base address. 39 registers are
used out of the 256 locations to control the output state of I/O pins, to read I/O pins, to set
the memory page, to control 8032 program and data address space, to control power
management, to READ/WRITE macrocells inside the General PLD, and other functions
during runtime. Unused locations within csiop are reserved and should not be accessed.
Memory page register
8032 MCU architecture has an inherent size limit of 64K bytes in either program address
space or XDATA space. Some UPSD34xx devices have much more memory that 64K, so
special logic such as this page register is needed to access the extra memory. This 8-bit
UPSD3422
UPSD3433 128 KB
UPSD3434 256 KB
UPSD3454 256 KB
Device
Table 157 on page 193
(bytes)
64 KB
Flash
Total
size
205). The base address of these 256 locations is referred to in this data
Main Flash memory
Individual
(bytes)
sector
16 KB
16 KB
32 KB
32 KB
size
Table 157 on page 193
for SRAM sizes.
Select signal)
Number of
4 (FS0-3)
8 (FS0-7)
8 (FS0-7)
8 (FS0-7)
sectors
(Sector
(bytes)
32 KB
32 KB
32 KB
32 KB
Flash
Total
for Secondary Flash sector sizes.
size
Secondary Flash memory
Individual
(bytes)
sector
8 KB
8 KB
8 KB
8 KB
size
4 (CSBOOT0-3)
4 (CSBOOT0-3)
4 (CSBOOT0-3)
4 (CSBOOT0-3)
(Sector Select
Number of
sectors
signal)
PSD module
(bytes)
SRAM
SRAM
193/300
32 KB
4 KB
8 KB
8 KB
size