UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 66

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

Interrupt system
13.1.9
66/300
USB interrupt
The USB interrupt has multiple sources. The ISR must read the USB interrupt flag registers
(UIF0-3) to determine the source of the interrupt.
The USB interrupt can be activated by any of the following four group of interrupt sources:
●
●
●
●
Table 18.
Table 19.
1. 1 = Enable Interrupt, 0 = Disable Interrupt.
Table 20.
Table 21.
EADC
Bit 7
Bit 7
5
4
3
2
1
0
7
6
5
4
EA
Bit
Bit
Global: the interrupt flag is set when any of the following events occurs: USB Reset,
USB Suspend, USB Resume, and End of Packet;
In FIFO: the interrupt flag is set when any of the End Point In FIFO becomes empty;
Out FIFO: the interrupt flag is set when any of the End Point Out FIFO becomes full;
and
In FIFO NAK: the interrupt flag is set when any of the End Point In FIFO is not ready for
an IN (in-bound) packet.
7
6
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
IE: interrupt enable register (SFR A8h, reset value 00h)
IE register bit definition
IEA: interrupt enable addition register (SFR A7h, reset value 00h)
IEA register bit definition
Symbol
Symbol
EADC
EPCA
ESPI
ESPI
Bit 6
Bit 6
ET2
ES0
ET1
EX1
ET0
EX0
ES1
EA
–
–
EPCA
Bit 5
Bit 5
ET2
R/W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R/W
R,W
R,W
R,W
R,W
Global disable bit. 0 = All interrupts are disabled. 1 = Each
interrupt source can be individually enabled or disabled by
setting or clearing its enable bit.
Do not modify this bit. It is used by the JTAG debugger for
instruction tracing. Always read the bit and write back the
same bit value when writing this SFR.
Enable Timer 2 Interrupt
Enable UART0 Interrupt
Enable Timer 1 Interrupt
Enable External Interrupt INT1
Enable Timer 0 Interrupt
Enable External Interrupt INT0
Enable ADC Interrupt
Enable SPI Interrupt
Enable Programmable Counter Array Interrupt
Enable UART1 Interrupt
Bit 4
Bit 4
ES0
ES1
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Bit 3
Bit 3
ET1
–
Function
Function
Bit 2
Bit 2
EX1
–
Bit 1
Bit 1
EI
ET0
2
C
EUSB
Bit 0
Bit 0
EX0