UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 245

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UPSD3433E-40T6

Manufacturer Part Number
UPSD3433E-40T6
Description
MCU 8BIT 8032 128KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433E-40T6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4906

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3433E-40T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
UPSD3433E-40T6
Manufacturer:
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0
UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.50
Port C structure
Port C supports the following operating modes on pins PC2, PC3, PC4, PC7:
See
Port C pins can also be configured in PSDsoft for other dedicated functions:
The remaining four pins (TDI, TDO, TCK, TMS) on Port C are dedicated to the JTAG
function and cannot be used for any other function. See
debug on page
Port C also supports the Open Drain output drive type options on pins PC2, PC3, PC4, and
PC7 using the csiop Drive Select registers.
Figure 86 on page 246
MCU I/O Mode
GPLD Output Mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4,
MCELLBC7
GPLD Input Mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7
Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount
of time required for JTAG ISP programming. These two pins must be used together for
this function, adding to the four standard JTAG signals. When TSTAT and TERR are
used, it is referred to as “6-pin JTAG”. PC3 and PC4 cannot be used for other functions
if they are used for 6-pin JTAG. See
page 257
PC3 can be used as an output to indicate when a Flash memory program or erase
operation has completed. This is specified in PSDsoft Express as
Ready/Busy (PC3) on page
for details.
257.
for detail.
215.
Section 28.6.1: JTAG ISP and JTAG debug on
Section 28.6.1: JTAG ISP and JTAG
Section 28.5.13:
PSD module
245/300

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