MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 121

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MC68HC908AB32CFU

Manufacturer Part Number
MC68HC908AB32CFU
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908AB32CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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8.6.1.2 SWI Instruction
MC68HC908AB32
Freescale Semiconductor
NOTE:
NOTE:
Rev. 1.1
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I-bit) in the
condition code register.
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
System Integration Module (SIM)
Figure 8-11. Interrupt Recognition Example
INT1
INT2
CLI
LDA
PSHH
PULH
RTI
PSHH
PULH
RTI
#$FF
INT1 INTERRUPT SERVICE ROUTINE
INT2 INTERRUPT SERVICE ROUTINE
System Integration Module (SIM)
Figure 8-11
BACKGROUND
ROUTINE
Technical Data
121

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