MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 327

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC908AB32
Freescale Semiconductor
NOTE:
—
Rev. 1.1
MISO — Master In/Slave Out
SS — Slave Select
TACH[1:0] — Timer A Channel I/O Bits
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module, TIMA, and SCI
module. However, the DDRE bits always determine whether reading
port E returns the states of the latches or the states of the pins. See
Table
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. See
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTE4/SS pin is available for general-purpose I/O. See
Control
bit in data direction register E (DDRE) has no effect on the PTE4/SS
pin.
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. See
11.10.4 TIMA Channel Status and Control
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See
SCI Control Register
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See
15.9.1 SCI Control Register
17-6.
Register. When the SPI is enabled as a slave, the DDRE4
16.14.1 SPI Control
Input/Output (I/O) Ports
1.
1.
Register.
Registers.
Input/Output (I/O) Ports
16.14.1 SPI
Technical Data
15.9.1
327