MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 135

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.4.2 Phase-Locked Loop (PLL) Circuit
9.4.2.1 PLL Circuits
MC68HC908AB32
Freescale Semiconductor
—
Rev. 1.1
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
The PLL consists of the following circuits:
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency f
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f
The VCO’s output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f
9.4.2.4 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
•
•
•
•
•
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
Clock Generator Module (CGM)
NOM
RDV
, (4.9152MHz) times a linear factor L, or (L)f
= f
RCLK
.
VRS
for more information).
RCLK
is equal to the nominal center-of-range
, and is fed to the PLL through a
Clock Generator Module (CGM)
VDV
= f
VCLK
Technical Data
VCLK
NOM
VRS
/N. (See
.
, is fed
.
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