MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 144

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MC68HC908AB32CFU

Manufacturer Part Number
MC68HC908AB32CFU
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908AB32CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Clock Generator Module (CGM)
9.6.1 PLL Control Register (PCTL)
Technical Data
144
Addr.
$001C
$001D
$001E
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Bandwidth Control
Register Name
PLL Control Register
PLL Programming
Register
Register
(PBWC)
(PCTL)
(PPG)
Address:
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 9-4. CGM I/O Register Summary
$001C
PLLIE
AUTO
Bit 7
MUL7
PLLIE
Bit 7
0
0
0
0
Clock Generator Module (CGM)
Figure 9-5. PLL Control Register (PCTL)
= Unimplemented
= Unimplemented
LOCK
MUL6
PLLF
PLLF
6
0
0
1
6
0
PLLON
PLLON
MUL5
ACQ
5
1
0
1
5
1
MUL4
BCS
BCS
XLD
4
0
0
0
4
0
VRS7
3
1
1
0
0
0
3
1
1
MC68HC908AB32
VRS6
Freescale Semiconductor
2
1
1
0
0
1
2
1
1
VRS5
1
1
1
0
0
1
1
1
1
Rev. 1.1
Bit 0
VRS4
Bit 0
1
1
0
0
0
1
1

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