MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 206

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer Interface Module B (TIMB)
12.5.4.3 PWM Initialization
Technical Data
206
NOTE:
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H:TBCH0L)
initially control the buffered PWM output. TIMB channel 0 status and
control register (TBSC0) controls and monitors the PWM signal from the
linked channels. MS0B takes priority over MS0A.
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH:TBMODL), write
3. In the TIMB channel x registers (TBCHxH:TBCHxL), write the
4. In TIMB channel x status and control register (TBSCx):
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
the value for the required PWM period.
value for the required pulse width.
TSTOP.
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or
a. Write 1 to the toggle-on-overflow bit, TOVx.
b. Write 1:0 (to clear output on compare) or 1:1 (to set output on
Timer Interface Module B (TIMB)
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. See
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See
MC68HC908AB32
Table
Freescale Semiconductor
Table
12-3.
12-3.
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Rev. 1.1