MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 179
MC68HC908AB32CFU
Manufacturer Part Number
MC68HC908AB32CFU
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AB32CFUE.pdf
(392 pages)
Specifications of MC68HC908AB32CFU
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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11.5.4.2 Buffered PWM Signal Generation
MC68HC908AB32
Freescale Semiconductor
NOTE:
—
Rev. 1.1
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TACH0 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTE2/TACH0 pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function, and TIMA channel 1
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O
pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTF0/TACH2 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The TIMA channel 2 registers
initially control the pulse width on the PTF0/TACH2 pin. Writing to the
TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (2 or
3) that control the pulse width are the ones written to last. TASC2
controls and monitors the buffered PWM function, and TIMA channel 3
status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O
pin.
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Technical Data
179
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