MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 133

IC MCU 8MHZ 32K FLASH 40-DIP

MC68HC908GP32CP

Manufacturer Part Number
MC68HC908GP32CP
Description
IC MCU 8MHZ 32K FLASH 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GP32CP

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908GP32CP
Manufacturer:
ROCKWELL
Quantity:
201
Part Number:
MC68HC908GP32CP
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
7.7 Interrupts
7.8 Special Modes
7.8.1 Wait Mode
MC68HC908GP32
MOTOROLA
NOTE:
MC68HC08GP32
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
The WAIT instruction puts the MCU in low power-consumption standby
modes.
The WAIT instruction does not affect the CGMC. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL) to save power. Less
power-sensitive applications can disengage the PLL without turning it
off, so that the PLL clock is immediately available at WAIT exit. This
would be the case also when the PLL is to wake the MCU from wait
mode, such as when the PLL is first enabled and waiting for LOCK or
LOCK is lost.
Rev. 6
Clock Generator Module (CGMC)
Clock Generator Module (CGMC)
Technical Data
Interrupts
131

Related parts for MC68HC908GP32CP