MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 201

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes:
V
V
GND
GND
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA7 = 0 → serial, PTA7 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
IRQ
V
V
GND
V
TST
TST
or
X
or
DD
DD
DD
RESET
GND
V
V
V
V
V
V
V
V
V
or
TST
or
TST
TST
or
TST
DD
DD
DD
DD
DD
(progra-
$FFFE/
$FFFF
(blank)
(blank)
(blank)
mmed)
$FF
$FF
$FF
$FF
Not
X
X
X
OFF
OFF
OFF
OFF
OFF
PLL
ON
X
Table 15-1. Monitor Mode Signal Requirements and Options
PTC0
X
X
X
X
X
1
1
PTC1
X
0
0
X
X
X
X
PTC3
X
0
1
X
X
X
X
External
Clock
4.9152
9.8304
9.8304
32.768
MHz
MHz
MHz
kHz
X
X
X
(1)
CGMOUT
4.9152
4.9152
4.9152
4.9152
MHz
MHz
MHz
MHz
—
—
0
Frequency
2.4576
2.4576
2.4576
2.4576
MHz
MHz
MHz
MHz
Bus
—
—
0
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
COP
PTA0
X
1
X
1
X
1
X
1
X
X
X
Communication
For Serial
PTA7
X
X
X
0
1
0
1
0
1
0
1
Rate
Baud
9600
9600
9600
9600
DNA
DNA
DNA
DNA
—
—
0
(2) (3)
No operation until
reset goes high
PTC0 and PTC1
voltages only required
if IRQ = V
PTC3 determines
frequency divider
PTC0 and PTC1
voltages only required
if IRQ = V
PTC3 determines
frequency divider
External frequency
always divided by 4
PLL enabled
(BCS set)
in monitor code
Enters user mode —
will encounter an
illegal address reset
Enters user mode
Comment
TST
TST
;
;