MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 365

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

22.10.5 TIM Channel Registers
MC68HC908GP32
MOTOROLA
NOTE:
NOTE:
•
MC68HC08GP32
Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
CHxMAX
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 22-11
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
TCHx
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
OVERFLOW
—
Rev. 6
Timer Interface Module (TIM)
COMPARE
PERIOD
OUTPUT
shows, the CHxMAX bit takes effect in the cycle after it
Figure 22-11. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer Interface Module (TIM)
OVERFLOW
COMPARE
OUTPUT
Technical Data
OVERFLOW
I/O Registers
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