MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 115

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MCHC908GR8AVFAE

Manufacturer Part Number
MCHC908GR8AVFAE
Description
IC MCU 8K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908GR8AVFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCHC908GR8AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 12
Input/Output (I/O) Ports
12.1 Introduction
Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or
outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices
if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port
bit is switched to output mode.
Freescale Semiconductor
Addr.
$0000
$0001
$0002
$0003
$0004
Data Direction Register A
Register Name
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
Connect any unused I/O pins to an appropriate logic level, either V
V
termination reduces excess current consumption and the possibility of
electrostatic damage.
Not all port pins are bonded out in all packages. Care sure be taken to make
any unbonded port pins an output to prevent them from being floating
inputs.
SS
See page 117.
See page 120.
See page 122.
See page 124.
See page 118.
. Although the I/O ports do not require termination for proper operation,
(DDRA)
(PTC)
(PTD)
(PTA)
(PTB)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Figure 12-1. I/O Port Register Summary
Bit 7
0
0
0
0
0
0
= Unimplemented
PTD6
6
0
0
0
0
0
NOTE
PTD5
PTB5
5
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
PTB4
PTD4
4
0
0
0
0
DDRA3
PTA3
PTB3
PTD3
3
0
0
DDRA2
PTA2
PTB2
PTD2
2
0
0
DD
or
DDRA1
PTA1
PTB1
PTC1
PTD1
1
0
DDRA0
PTA0
PTB0
PTC0
PTD0
Bit 0
0
115

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