MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 193

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

OVRF — Overflow Bit
MODF — Mode Fault Bit
SPTE — SPI Transmitter Empty Bit
MODFEN — Mode Fault Enable Bit
SPR1 and SPR0 — SPI Baud Rate Select Bits
Freescale Semiconductor
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
MODFEN set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set
and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request if SPTIE in the SPI control register is set
also.
During an SPTE CPU interrupt, the CPU clears SPTE bit writing to the transmit data register. Reset
sets the SPTE bit.
This read/write bit, when set, allows the MODF flag to be set. If the MODF flag is set, clearing
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is 0,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is 1, then the SS is not available as a general-purpose I/O. When the SPI is enabled
as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN.
See
If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See
Error.
In master mode, these read/write bits select one of four baud rates as shown in
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
1 = Overflow
0 = No overflow
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
1 = Transmit data register empty
0 = Transmit data register not empty
15.11.4 SS (Slave Select).
Do not write to the SPI data register unless SPTE is high.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Table 15-3. SPI Master Baud Rate Selection
SPR1 and SPR0
00
01
10
11
NOTE
Baud Rate Divisor (BD)
128
32
2
8
Table
15.6.2 Mode Fault
15-3. SPR1 and
I/O Registers
193