MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 67

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PRE1 and PRE0 — Prescaler Program Bits
VPR1 and 0 — VCO Power-of-Two Range Select Bits
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
Freescale Semiconductor
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
Circuits
Reset clears these bits.
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See
Register.) controls the hardware center-of-range frequency, f
the PLLON bit is set. Reset clears these bits.
•
•
•
•
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
and
Address: $0037
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector
4.3.3 PLL
Programming the
Reset:
Read:
Write:
1. Do not program E to a value of 3.
PRE1 and PRE0
VPR1 and VPR0
Figure 4-5. PLL Bandwidth Control Register (PBWC)
AUTO
Bit 7
0
Circuits,
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Table 4-2. PRE 1 and PRE0 Programming
00
01
10
11
00
01
10
11
Table 4-3. VPR1 and VPR0 Programming
= Unimplemented
LOCK
PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set.
6
0
4.3.6 Programming the
ACQ
Circuit.)
5
0
3
P
E
0
1
2
3
0
1
2
R
(1)
4
0
0
= Reserved
PLL, and
3
0
0
VRS
Prescaler Multiplier
VCO Power-of-Two
. VPR1:VPR0 cannot be written when
Range Multiplier
4.5.5 PLL VCO Range Select
2
0
0
1
2
4
8
1
2
4
8
1
0
0
Bit 0
R
0
CGM Registers
PLL
67