MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 203

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
17.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
Freescale Semiconductor
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
Addr.
↓
Timer 2 Channel 0 Status and
Control Register (T2SC0)
Register High (T2MODH)
Register High (T2CNTH)
Register High (T2CH0H)
Timer 2 Counter Modulo
Timer 2 Counter Modulo
Register Low (T2MODL)
Register Low (T2CNTL)
Register Low (T2CH0L)
Register Name
Timer 2 Channel 0
Timer 2 Channel 0
Timer 2 Counter
Timer 2 Counter
See page 210.
See page 210.
See page 211.
See page 211.
See page 211.
See page 214.
See page 214.
Reserved
Reserved
Figure 17-3. TIM I/O Register Summary (Sheet 2 of 2)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Bit 15
Bit 15
CH0F
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
R
R
0
0
1
1
0
0
0
= Unimplemented
CH0IE
14
14
14
R
R
6
0
6
0
1
6
1
0
6
0
MS0B
13
13
13
R
R
5
0
5
0
1
5
1
0
5
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
12
12
12
R
R
4
0
4
0
1
4
1
0
4
0
ELS0B
11
11
11
R
R
3
0
3
0
1
3
1
0
3
0
ELS0A
10
10
10
R
R
2
0
2
0
1
2
1
0
2
0
Functional Description
TOV0
R
R
1
9
0
1
0
9
1
1
1
0
9
1
0
CH0MAX
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
R
R
0
0
1
1
0
0
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