MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 65

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-3
Freescale Semiconductor
$0036
$0037
$0038
$0039
$003A
$003B
Addr.
NOTES:
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•
•
•
•
•
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL control register (PCTL)
(See
PLL bandwidth control register (PBWC)
(See
PLL multiplier select register high (PMSH)
(See
PLL multiplier select register low (PMSL)
(See
PLL VCO range select register (PMRS)
(See
PLL reference divider select register (PMDS)
(See
PLL Multiplier Select High
PLL Multiplier Select Low
Select Register (PMDS)
PLL VCO Select Range
is a summary of the CGM registers.
PLL Bandwidth Control
PLL Reference Divider
Register Name
4.5.1 PLL Control
4.5.2 PLL Bandwidth Control
4.5.3 PLL Multiplier Select Register
4.5.4 PLL Multiplier Select Register
4.5.5 PLL VCO Range Select
4.5.6 PLL Reference Divider Select
PLL Control Register
Register (PBWC)
Register (PMSH)
Register (PMRS)
Register (PMSL)
(PCTL)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 4-3. CGM I/O Register Summary
Register.)
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
Register.)
= Unimplemented
Register.)
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
High.)
Low.)
Register.)
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
MUL4
VRS4
BCS
R
4
0
0
0
0
0
0
0
0
0
= Reserved
MUL11
MUL3
RDS3
PRE1
VRS3
3
0
0
0
0
0
0
0
MUL10
MUL2
RDS2
PRE0
VRS2
2
0
0
0
0
0
0
0
VPR1
MUL9
MUL1
RDS1
VRS1
1
0
0
0
0
0
0
0
CGM Registers
VPR0
MUL8
MUL0
VRS0
RDS0
Bit 0
R
0
0
0
0
0
1
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