MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 209

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TOF — TIM Overflow Flag Bit
TOIE — TIM Overflow Interrupt Enable Bit
TSTOP — TIM Stop Bit
TRST — TIM Reset Bit
PS[2:0] — Prescaler Select Bits
Freescale Semiconductor
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as 0. Reset clears the TRST bit.
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 17-2
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
1 = TIM counter stopped
0 = TIM counter active
1 = Prescaler and TIM counter cleared
0 = No effect
Address: T1SC, $002 and T2SC, $002B
shows. Reset clears the PS[2:0] bits.
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. Also, when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
Reset:
Read:
Write:
Bit 7
TOF
Figure 17-5. TIM Status and Control Register (TSC)
0
0
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
= Unimplemented
TOIE
6
0
TSTOP
5
1
NOTE
NOTE
TRST
4
0
0
3
0
0
PS2
2
0
PS1
1
0
Bit 0
PS0
0
I/O Registers
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