CY8C3446LTI-073 Cypress Semiconductor Corp, CY8C3446LTI-073 Datasheet - Page 10

• Manufacturer Part Number: CY8C3446LTI-073
• Description: IC MCU 8BIT 64KB FLASH 48QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446LTI-073

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: QFN EP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

3. Pin Descriptions
IDAC0, IDAC2
Low resistance output pin for high current DACs (IDAC).
OpAmp0out, OpAmp2out
High current output of uncommitted opamp
Extref0, Extref1
External reference input to the analog system.
OpAmp0–, OpAmp2–
Inverting input to uncommitted opamp.
OpAmp0+, OpAmp2+
Noninverting input to uncommitted opamp.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense
I2C0: SCL, I2C1: SCL
I
Any I/O pin can be used for I
required.
I2C0: SDA, I2C1: SDA
I
Any I/O pin can be used for I
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
Document Number: 001-53304 Rev. *K
Note
2
2
12. GPIOs with opamp outputs are not recommended for use with CapSense.
C SCL line providing wake from sleep on an address match.
C SDA line providing wake from sleep on an address match.
[12]
.
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
2
2
C SCL if wake from sleep is not
C SDA if wake from sleep is not
Plane
Vssd
[12]
Vddd
.
Vssd
Vssa
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25-MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK
Serial wire debug clock programming and debug port
connection.
SWDIO
Serial wire debug input and output programming and debug port
connection.
SWV.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data In programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
Vdda
Plane
Vssa
PSoC
®
3: CY8C34 Family
Data Sheet
Page 10 of 126
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