MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 122

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Debug Support
5.3.1
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data
output.
Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses
associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions,
JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception
vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the MCF5272 uses the debug pins to output the following sequence of
information on successive processor clock cycles:
5-4
0x8–
Hex
0xB
0xC
0xD
0xE
0xF
PST[3:0]
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA
3. The new target address is optionally available on subsequent cycles using the DDATA port. The
pins. Encodings 0x9–0xB identify the number of bytes displayed.
number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes).
Binary
1000–
1011
1100
1101
1110
1111
Begin Execution of Taken Branch (PST = 0x5)
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The value is
driven onto the PST port one PSTCLK cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a
different encoding, as described below. Because the 0xC encoding defines a multiple-cycle mode, PST
outputs are driven with 0xC until exception processing completes.
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace). Because this
encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing
completes.
Processor is stopped. Appears in multiple-cycle format when the MCF5272 executes a STOP instruction. The
ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped
mode is exited
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until
the processor is restarted or reset. (see
MCF5272 ColdFire
.
Table 5-2. Processor Status Encoding (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Section 5.5.1, “CPU
Definition
Halt”)
Freescale Semiconductor