MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 305

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

13.2.4.1
The port automatically retransmits the received data on a bit-by-bit basis in this mode. The local
CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. While in
this mode, received data is clocked on the receiver clock and retransmitted on transmit Dout pin.
13.2.4.2
TxData is internally connected to RxData in this mode. This mode is useful for testing the operation of a
local port by sending data to the transmitter and checking data assembled by the receiver. In this manner,
correct channel operations can be assured. Also, both transmitter and CPU-to-receiver communications
continue normally in this mode. While in this mode, the receive Din pin is ignored, the transmit Dout is
held marking, and the receiver is clocked by the transmitter clock.
13.2.4.3
The channel automatically transmits received data on the transmit Dout pin on a bit-by-bit basis in this
mode. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter
operation of a remote channel. While in this mode, the receiver clock is used for the transmitter.
13.2.5
The PLIC module generates two interrupts—the periodic frame interrupt and the aperiodic status interrupt.
13.2.5.1
The frame interrupt is a periodic 2-KHz interrupt as shown in
rate for servicing the incoming and outgoing B and D channels. This service routine must execute in a
timely manner. Each of the B- and D-channel transmit and receive registers should be written and read
prior to the next 2-KHz interrupt for underrun or overrun conditions to be prevented.
Freescale Semiconductor
CPU
GCI/IDL Interrupts
Automatic Echo Mode
Local Loopback Mode
Remote Loopback Mode
GCI/IDL Periodic Frame Interrupt
Disabled
(a) Automatic Echo
MCF5272 ColdFire
Rx
Tx
CPU
Disabled
Disabled
Disabled
Figure 13-9. GCI/IDL Loopback Mode
(c) Remote Loopback
®
Integrated Microprocessor User’s Manual, Rev. 3
Rx
Tx
Dout
Din
Disabled
Disabled
CPU
Din
Dout
Figure
(b) Local Loopback
13-10. This is the normal interrupt
Rx
Tx
Physical Layer Interface Controller (PLIC)
Disabled
Disabled
Din
Dout
13-9