MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 382

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

UART Modules
Once enabled, the autobaud detector can calculate the transmission rate only once. If a new calculation is
required, UCR[ENAB] must first be cleared and then set again. Thus, a new UART connection cannot be
hot-plugged into an active UART connection if that connection is operating at a different rate without first
reinitializing the autobaud detector.
16.5.2
Figure 16-24
operating registers, which are described generally in the following sections and described in detail in
Section 16.3, “Register
16.5.2.1
The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a
character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the CPU to a serial
bit stream on TxD. It automatically sends a start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the
transmitter output on the falling edge of the clock source.
After the stop bits are sent, if no new character is in the transmitter holding register, the TxD output
remains high (mark condition) and the transmitter empty bit, USRn[TxEMP], is set. Transmission resumes
and TxEMP is cleared when the CPU loads a new character into the UART transmitter buffer (UTBn). If
the transmitter receives a disable command, it continues until any character in the transmitter shift register
is completely sent.
16-22
UART Transmit
UART Receive
FIFO (URB)
FIFO (UTB)
(24 Bytes)
(24 Bytes)
Transmitter and Receiver Operating Modes
Transmitting
is a functional block diagram of the transmitter and receiver showing the command and
MCF5272 ColdFire
Figure 16-24. Transmitter and Receiver Functional Diagram
Descriptions.”
Receiver FIFO
UART Command Register (UCR0)
UART Mode Register 1 (UMR1)
UART Mode Register 2 (UMR2)
UART Status Register (USR0)
Transmitter FIFO
Receiver Shift Register
Transmitter Shift Register
®
Integrated Microprocessor User’s Manual, Rev. 3
UART
R/W
R/W
R
W
W
R
Freescale Semiconductor
External
Interface
RXD
TXD