MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 534

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Index
Pin descriptions,
Pipelines
PLIC
Index-4
address bus,
byte strobes,
clock,
data bus,
dynamic data bus sizing,
general-purpose I/O ports,
interrupt request inputs,
JTAG test access port and BDM debug port,
operating mode configuration,
PLI TDM ports,
power supply,
QSPI signals, 19-29–??
RSTI,
SDRAM
UART0 module signals,
USB module signals and PA,
instruction fetch,
operand execution,
aperiodic status register,
application examples,
automatic echo mode,
B1 data
B2 data
B-Channel
clock select register,
clock synthesis,
D data
D-Channel
D-Channel request register,
D-Channel status register,
frame sync synthesis,
GCI C/I channel
GCI interrupts aperiodic status,
bank selects,
clock enable,
column address strobe,
row address 10,
row address strobe,
write enable,
receive registers,
transmit registers,
receive registers,
transmit registers,
HDLC encoded data,
unencoded data,
receive registers,
transmit registers,
HDLC encoded data,
unencoded data,
receive registers,
transmit registers,
transmit status register,
19-25
19-23
19-19
19-19
19-20
19-38
??–19-38
19-23
19-22
19-22
13-11
19-30–19-35
2-2
19-23
13-5
13-7
2-2
13-15
13-16
13-16
13-28
13-17
13-17
13-18
13-29
13-34
13-13
19-22
13-35–13-42
13-9
13-6
13-6
MCF5272 ColdFire
19-23
19-24–19-25
13-23
19-19
19-22
13-30
13-31
19-24
13-32
19-25–19-27
19-37
13-10
®
19-35–19-37
Integrated Microprocessor User’s Manual, Rev. 3
Ports
Power management registers,
Program counter,
Programming model
Programming models
PST outputs,
PULSE instruction,
PWM
GCI monitor channel
GCI/IDL
initialization,
interrupt configuration
interrupt control,
introduction,
local loopback mode,
loopback control register,
periodic status registers,
port configuration
register memory map,
registers, general,
remote loopback mode,
super frame sync generation,
sync delay registers,
timing generator,
parallel input/output,
PWM,
QSPI,
Ethernet,
instruction cache,
MAC,
overview,
ROM,
SIM,
SRAM,
supervisor, 2-7,
user,
control register,
operation,
overview,
receive registers,
transmit abort register,
transmit registers,
transmit status register,
B- and D-Channel
B- and D-Channel bit alignment,
block,
D-Channel contention,
looping modes,
periodic frame interrupts,
example,
registers,
example,
registers,
receive data registers,
transmit data registers,
2-4
6-2
14-9
2-7
4-5
18-2
4-2
13-3
11-10
2-4
18-1
18-2
5-3
13-37
13-20
13-35
13-18
13-1
13-35
2-6
2-7
18-3
13-11
13-11
5-3
4-12
13-8
13-15
13-24
13-25
13-33
1-6
13-9
13-13
13-9
13-22
13-26
13-8
13-27
13-20
13-3
6-7
13-4
13-9
13-13
Freescale Semiconductor
13-5