MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 86

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

ColdFire Core
Table 2-8
1
2-18
CPUSHL
HALT
MOVE from SR
MOVE to SR
MOVEC
RTE
STOP
WDEBUG
1
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TRAP
TRAPF
TST
UNLK
WDDATA
Instruction
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution
by setting CSR[UHE].
Instruction
1
describes supervisor-mode instructions.
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
#<vector>
None
#<data>
<ea>y
Ax
<ea>y
Operand Syntax
(bc),(Ax)
none
SR, Dx
Dy,SR
#<data>,SR
Ry,Rc
None
#<data>
<ea-2>y
Operand Syntax
MCF5272 ColdFire
Table 2-7. User-Mode Instruction Set Summary (continued)
Table 2-8. Supervisor-Mode Instruction Set Summary
.L
.L
.L
.L
.L
.L
.W
Unsized
Unsized
.W
.L
.B,.W,.L
Unsized
.B,.W,.L
Unsized
Unsized
.W
.W
.L
Unsized
.W
.L
Operand Size
Operand Size
®
Integrated Microprocessor User’s Manual, Rev. 3
Invalidate instruction cache line
Enter halted state
SR → Dx
Source → SR
Ry → Rc
Rc
0x002
0x004
0x005
0x801
0xC00
0xC04
0xC0F
(SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield ⎯ SP
Immediate data → SR; enter stopped state
<ea-2>y → debug module
Destination – source → destination
Destination – source → destination
Destination – immediate data → destination
Destination – immediate data → destination
Destination – source – X → destination
MSW of Dx ←→ LSW of Dx
SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; format → (SP);
Vector address → PC
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
Set condition codes
Ax →SP; (SP) → Ax; SP + 4 → SP
<ea>y →DDATA port
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Vector base register (VBR)
ROM base address register (ROMBAR)
RAM base address register (RAMBAR)
Module base address register (MBAR)
Operation
Operation
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