MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 390

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

UART Modules
16.5.6
The software flowchart,
16.5.6.1
Figure 16-31
16-30
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•
•
UART module initialization—These routines consist of SINIT and CHCHK (sheets 1 and 2).
Before SINIT is called at system initialization, the calling routine allocates 2 words on the system
stack. On return to the calling routine, SINIT passes UART status data on the stack. If SINIT finds
no errors, the transmitter and receiver are enabled. SINIT calls CHCHK to perform the checks.
When called, SINIT places the UART in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
I/O driver routine—This routine (sheets 4 and 5) consists of INCH, the terminal input character
routine which gets a character from the receiver, and OUTCH, which sends a character to the
transmitter.
Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART module
generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the
interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt
source again, then returns from exception processing to the system monitor.
Programming
UART Module Initialization Sequence
shows the UART module initialization sequence.
UART module registers can be accessed by word or byte operations, but
only data byte D[7:0] is valid.
Figure 16-31. UART Mode Programming Flowchart (Sheet 1 of 5)
MCF5272 ColdFire
Figure
16-31, consists of the following:
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
Freescale Semiconductor