XR17D154IV-F Exar Corporation, XR17D154IV-F Datasheet - Page 11

• Manufacturer Part Number: XR17D154IV-F
• Description: IC UART PCI BUS QUAD 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D154IV-F

• Number Of Channels: 4, QUART
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1290

xr
REV. 1.2.2
A
0x18h
DDRESS
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x20
0x24
0x28
31:16
15:0
31:28
27
26:25
24
23
22:16
15:9,7,
5,4,3,2
8
6
1
0
31:8
7:0
31:24
23:16
15:8
7:0
31:11
10:0
31:0
31:0
31:0
31:0
31:0
31:0
31:16
B
ITS
R-Reset
RWR
RWR
RWR
RWR
T
WO
WO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1
1
1
2: PCI L
Device ID (Exar device ID number or from EEPROM)
Vendor ID (Exar ID or from EEPROM) specified by PCISIG
Status bits (error reporting bits)
Target Abort. Set whenever D154 terminates with a target abort.
DEVSEL# timing.
Unimplemented bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bits
Command bits (reserved)
SERR# driver enable. Logic 1=enable driver and 0=disable
driver
Parity error enable. Logic 1=respond to parity error and 0=ignore
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
Command controls a device’s response to I/O space accesses:
0 = disable I/O space accesses 1 = enable I/O space accesses
Class Code (Simple 550 Communication Controller).
Revision ID (Exar device revision number)
BIST (Built-in Self Test)
Header Type (a single function device with one BAR)
Unimplemented Latency Timer (needed only for bus master)
Unimplemented Cache Line Size
Memory Base Address Register (BAR)
Claims a 2K address space for the memory mapped UARTs
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Reserved
Subsystem ID (write from external EEPROM by customer)
OCAL
B
US
C
ONFIGURATION
11
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
D
ESCRIPTION
S
PACE
R
EGISTERS
Current Rev. value
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
ESET
0x070002
000 0000
0x13A8
0xX000
0x0154
0x0000
0x0000
XR17D154
(
0000
0x00
0x00
0x00
0x00
0x00
HEX
00
0
0
1
0
0
0
0
V
ALUE
)