XR17D154IV-F Exar Corporation, XR17D154IV-F Datasheet - Page 25

• Manufacturer Part Number: XR17D154IV-F
• Description: IC UART PCI BUS QUAD 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D154IV-F

• Number Of Channels: 4, QUART
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1290

xr
REV. 1.2.2
The XR17D154 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), and 0x780 (channel 3). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
4.1.2
Data Bit-31
WITH N
Data Bit-31
WITH LSR
Read n+0 to n+3
Read n+4 to n+7
Read n+0 to n+1
Read n+2 to n+3
PCI Bus
R
R
PCI Bus
EAD
EAD
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Etc.
Receive Data Byte n+1
RX FIFO,
RX FIFO,
Receive Data Byte n+3
Etc
O
Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780
E
E
RRORS
RRORS
Channel 0 to 3 ReceiveData in 32-bit alignment through the Configuration Register Address
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
FIFO Data n+3
FIFO Data n+7
FIFO Data n+1
FIFO Data n+3
B
B
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
Line Status Register n+1
Receive Data Byte n+2
3
3
the Configuration Register Address 0x0180 and 0x0380
0x0100, 0x0300, 0x0500 and 0x0700
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
B
B
YTE
YTE
25
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+1
Receive Data Byte n+0
FIFO Data n+1
FIFO Data n+5
FIFO Data n+0
FIFO Data n+2
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+0
Line Status Register n+0
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
B
B
YTE
YTE
XR17D154
Data Bit-0
PCI Bus
Data Bit-0
0
0
PCI Bus