XR17D154IV-F Exar Corporation, XR17D154IV-F Datasheet - Page 17

• Manufacturer Part Number: XR17D154IV-F
• Description: IC UART PCI BUS QUAD 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D154IV-F

• Number Of Channels: 4, QUART
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1290

xr
REV. 1.2.2
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for continue interval. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
TIMERCNTL [0]
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [4]
TIMERCNTL [7:5]
2.2.2
F
IGURE
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
0
X
XX-XX-00-00)
7. T
TIMERCNTL [3]
TIMERCNTL [1]
TIMERCNTL [2]
TIMERCNTL [0]
TIMERCNTL [4]
TIMERMSB and TIMERLSB
OSC. CLOCK
IMER
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
Reserved (defaults to zero)
TMRCK
(16-bit Value)
/C
OUNTER CIRCUIT
T
Timer Interrupt Enable
Start/Stop
Single/Re-triggerable
Clock
Select
ABLE
1
0
7: UART C
T
ABLE
.
8: TIMER CONTROL R
Timer/Counter
HANNEL
16-Bit
Re-trigger
17
[3:0] I
0
1
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
Time-out
Single-shot
NTERRUPT
EGISTERS
1
0
No Interrupt
C
Timer Interrupt, Ch-0 INT=7
LEARING
1
0
:
MPIOLVL[0]
MPIO[0]
XR17D154
DEFAULT