AD9857AST Analog Devices Inc, AD9857AST Datasheet - Page 15

• Manufacturer Part Number: AD9857AST
• Description: IC QUADRATURE DGTL UPCONV 80LQFP
• Manufacturer: Analog Devices Inc
• Series: AD9857r

Specifications of AD9857AST

• Rohs Status: RoHS non-compliant
• Function: Upconverter
• Frequency: 5MHz ~ 200MHz
• Rf Type: HFC Cable Network
• Package / Case: 80-LQFP

MODES OF OPERATION
The AD9857 has three operating modes:
•
•
•
Mode selection is accomplished by programming a control
register via the serial port. The inverse SINC filter and output
scale multiplier are available in all three modes.
QUADRATURE MODULATION MODE
In quadrature modulation mode, both the I and Q data paths
are active. A block diagram of the AD9857 operating in the
quadrature modulation mode is shown in Figure 18.
In quadrature modulation mode, the PDCLK/FUD pin is an
output and functions as the parallel data clock (PDCLK), which
serves to synchronize the input of data to the AD9857. In this
mode, the input data must be synchronized with the rising edge
Quadrature modulation mode (default)
Single-tone mode
Interpolating DAC mode
PARALLEL
DATA IN
(14-BIT)
PDCLK/
FUD
14
14
Q
I
TxENABLE
CIC FILTER
INVERSE
INV
CIC
RESET
OVERFLOW
POLATOR
CIC
INTER-
FIXED
(4 )
CONTROL REGISTERS
PROGRAMMABLE
SERIAL
INTERPOLATOR
PORT
Figure 18. Quadrature Modulation Mode
(2 - 63 )
CIC
POWER-
POWER-
DIGITAL
Rev. C| Page 15 of 40
DOWN
LOGIC
DOWN
TUNING
WORD
QUADRATURE
TIMING AND CONTROL
MODULATOR
PROFILE
PS1
SELECT
LOGIC
CORE
DDS
PS0
of PDCLK. The PDCLK operates at twice the rate of either the I
or Q data path. This is due to the fact that the I and Q data must
be presented to the parallel port as two 14-bit words
multiplexed in time. One I word and one Q word together
comprise one internal sample. Each sample is propagated along
the internal data pathway in parallel fashion.
The DDS core provides a quadrature (sin and cos) local
oscillator signal to the quadrature modulator, where the I and Q
data are multiplied by the respective phase of the carrier and
summed together, to produce a quadrature-modulated data
stream.
All of this occurs in the digital domain, and only then is the
digital data stream applied to the 14-bit DAC to become the
quadrature-modulated analog output signal.
32
INVERSE
FILTER
SINC
MULTIPLIER
(4 – 20 )
CLOCK
LOCK
PLL
14
AD9857
OUTPUT
SCALE
VALUE
8
CONTROL
CLOCK
MODE
14-BIT
INPUT
MODE
DAC
DAC_RSET
IOUT
IOUT
REFCLK
REFCLK
AD9857