AD9857AST Analog Devices Inc, AD9857AST Datasheet - Page 16

IC QUADRATURE DGTL UPCONV 80LQFP

AD9857AST

Manufacturer Part Number
AD9857AST
Description
IC QUADRATURE DGTL UPCONV 80LQFP
Manufacturer
Analog Devices Inc
Series
AD9857r
Datasheet

Specifications of AD9857AST

Rohs Status
RoHS non-compliant
Function
Upconverter
Frequency
5MHz ~ 200MHz
Rf Type
HFC Cable Network
Package / Case
80-LQFP

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AD9857
SINGLE-TONE MODE
A block diagram of the AD9857 operating in the single-tone
mode is shown in Figure 19. In the single-tone mode, both the
I and Q data paths are disabled from the 14-bit parallel data
port up to and including the modulator. The PDCLK/ FUD pin
is an input and functions as a frequency update (FUD) control
signal. This is necessary because the frequency tuning word is
programmed via the asynchronous serial port. The FUD signal
causes the new frequency tuning word to become active.
In single-tone mode, the cosine portion of the DDS serves as
the signal source. The output signal consists of a single
frequency as determined by the tuning word stored in the
appropriate control register, per each profile.
PDCLK/
FUD
AD9857
RESET
CONTROL REGISTERS
SERIAL
PORT
POWER-
POWER-
DIGITAL
DOWN
LOGIC
DOWN
TIMING AND CONTROL
Figure 19. Single-Tone Mode
TUNING
WORD
PROFILE
PS1
SELECT
Rev. C | Page 16 of 40
LOGIC
CORE
DDS
PS0
32
In the single-tone mode, no 14-bit parallel data is applied to the
AD9857. The internal DDS core is used to produce a single
frequency signal according to the tuning word. The single-tone
signal then moves toward the output, where the inverse SINC
filter and the output scaling can be applied. Finally, the digital
single-tone signal is converted to the analog domain by the
14-bit DAC.
INVERSE
FILTER
SINC
MULTIPLIER
(4 – 20 )
CLOCK
LOCK
PLL
14
OUTPUT
SCALE
VALUE
8
CONTROL
CLOCK
14-BIT
MODE
INPUT
MODE
DAC
DAC_RSET
IOUT
IOUT
REFCLK
REFCLK

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