MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 114

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.12.4
In Beacon-Enabled mode, the TX GTSx FIFOs are
used for the transmission of data or MAC command
frames during the CFP of the superframe. Refer to
Section 3.8.1 “Beacon-Enabled Network” for more
information
Beacon-Enabled mode.
FIGURE 3-14:
2.
3.
4.
5.
DS39776C-page 114
MRF24J40
Memory Address
Memory Address
Packet Structure
If the packet requires an Acknowledgment, the
Acknowledgment request bit in the frame control
field should be set to ‘1’ in the MAC Header
(MHR) when the host microcontroller loads the
respective TX GTSx FIFO, and set the
TXG1ACKREQ
TXG2ACKREQ (TXG2CON 0x1D<2>) bit = 1.
Refer to Section 3.13 “Acknowledgement” for
more
configuration.
Program the number of retry times for the
respective TX GTSx FIFO in the TXG1RETRY
(TXG1CON
(TXG2CON 0x1D<7:6>) bits.
If the frame is to be encrypted, the security
enabled bit in the frame control field should be
set to ‘1’ in the MAC Header (MHR) when the
host microcontroller loads the TX GTSx FIFO,
and
0x1C<1>)
0x1D<1>) bit = 1. Refer to Section 3.17 “Secu-
rity” for more information about Security
modes.
Program the slot number for the respective TX
GTSx FIFO in the TXG1SLOT (TXG1CON
0x1C<5:3>
0x1D<5:3>) bits.
TX GTS1 FIFO
TX GTS2 FIFO
set
TX GTSx FIFO
information
octets
about
the
or
0x1C<7:6>)
or
Header
Length
TX GTS1 AND GTS2 FIFOS FORMAT
0x100
0x180
(TXG1CON
guaranteed
TXG2SECEN
TXG1SECEN
(m)
1
TXG2SLOT
about
(m + n)
Length
Frame
0x101
0x181
1
or
Acknowledgment
0x1C<2>)
time
TXG2RETRY
0x102 – (0x102 + m – 1)
0x182 – (0x182 + m – 1)
(TXG1CON
(TXG2CON
(TXG2CON
slots
Header
m
or
Preliminary
in
To transmit a packet in the TX GTSx FIFO, perform the
following steps:
1.
6.
7.
The host processor loads the respective TX
GTSx FIFO with an IEEE 802.15.4 compliant
data or MAC command frame using the format
shown in Figure 3-14.
Transmit the packet in the respective TX GTSx
FIFO by setting the TXG1TRIG (TXG1CON
0x1C<0>) or TXG2TRIG (TXG2CON 0x1D<0>)
bit = 1. The bit will be automatically cleared by
hardware. The packet will be transmitted at the
corresponding slot time of the superframe.
A TXG1IF (INTSTAT 0x31<1>) or TXG2IF
(INTSTAT 0x31<2>) interrupt will be issued. The
TXG1STAT (TXSTAT 0x24<1>) or TXG2STAT
(TXSTAT 0x24<2>) bit indicates the status of the
transmission:
TXGxSTAT = 0: Transmission was successful
TXGxSTAT = 1: Transmission
The number of retries of the most recent
transmission is contained in the TXG1RETRY
(TXG1CON
(TXG2CON 0x1D<7:6>) bits. The CCAFAIL
(TXSTAT 0x24<5>) bit = 1 indicates if the failed
transmission was due to the channel busy
(CSMA-CA timed out). The TXG1FNT (TXSTAT
0x24<3>) or TXG2FNT (TXSTAT 0x24<4>)
bit = 1 indicates if the TX GTSx FIFO transmis-
sion failed due to not enough time to transmit in
the guaranteed time slot.
(0x102 + m) – (0x102 + m + n – 1)
(0x182 + m) – (0x182 + m + n – 1)
0x1C<7:6>)
Payload
count exceeded
© 2010 Microchip Technology Inc.
n
or
failed,
TXG2RETRY
retry