MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 130

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.17.2
To receive and decrypt a secured frame from the
RXFIFO, perform the following steps:
1.
FIGURE 3-22:
2.
3.
TABLE 3-25:
DS39776C-page 130
MRF24J40
RX FIFO
RXFIFO Address:
When a packet is received and the security
enable bit = 1 in the frame control field, the
If the decryption should be ignored, set the
SECIGNORE (SECCON0 0x2C<7>) bit = 1.
The encrypted packet can be discarded or read
from the RXFIFO and processed in the upper
layers.
The host microcontroller loads the security key
into the RX FIFO Security Key memory location
as shown in Table 3-25.
RXFIFO
FIFO
MAC SUBLAYER RECEIVE
DECRYPTION
(m+n+2)
AND CONTROL REGISTER
BITS
Length
0x300
DECRYPTION SECURITY KEY
Frame
1
SECURITY RX FIFO FORMAT
Security Key Memory
0x301 to (0x301 + m – 1)
0x2B0-0x2BF
Header (MHR)
Address
m
Preliminary
(0x301 + m) to (0x301 + m + n – 1)
Data Payload (MSDU)
4.
5.
6.
7.
Note:
n
MRF24J40 issues a Security Interrupt, SECIF
(INTSTAT 0x31<4>). The Security Interrupt
indicates to the host microcontroller that the
received frame was secured. The host micro-
controller can choose to decrypt or ignore the
frame. The format of the received frame is
shown in Example 3-22.
Select the security suite and program the
RXCIPHER (SECCON0 0x2C<5:3>) bits. The
security suite selection values are shown in
Table 3-24.
Start the decryption by setting the SECSTART
(SECCON0 0x2C<6>) bit = 1.
When the decryption process is complete, a
Receive Interrupt (RXIF 0x31<3>) is issued.
Check the decryption status by reading
SECDECERR (RXSR 0x30<2>)
SECDECERR = 0: No Decryption Error
SECDECERR = 1: Decryption Error
If decryption error has occurred and the
packet in the FIFO needs to be discarded,
then set RXFLUSH (RXFLUSH 0x0D<0>)
bit = 1.
FCS
© 2010 Microchip Technology Inc.
2
(0x301 + m + n) to (0x301 + m + n + 1)
LQI
1
(0x301 + m + n + 2)
RSSI
1
(0x301 + m + n + 3)
octets