MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 91

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3
The MRF24J40 has one interrupt (INT) pin 16 that
signals one of eight interrupt events to the host
microcontroller. The interrupt structure is shown in
Figure 3-1. Interrupts are enabled via the INTCON
(0x32) register. Interrupt flags are located in the
INTSTAT (0x31) register. The INTSTAT register
clears-to-zero
microcontroller should read and store the INTSTAT
register and check the bits to determine which interrupt
occurred. The INT pin will continue to signal an
FIGURE 3-1:
TABLE 3-3:
© 2010 Microchip Technology Inc.
0x211 SLPCON0
Addr.
0x31 INTSTAT
0x32 INTCON
Interrupts
Name
INTSTAT.HSYMTMRIF
INTCON.HSYMTMRIE
upon
INTSTAT.WAKEIF
INTCON.WAKEIE
INTSTAT.TXG2IF
INTCON.TXG2IE
INTSTAT.TXG1IF
INTCON.TXG1IE
REGISTERS ASSOCIATED WITH INTERRUPTS
INTSTAT.SECIF
INTCON.SECIE
INTSTAT.TXNIF
INTCON.TXNIE
INTSTAT.SLPIF
INTCON.SLPIE
INTSTAT.RXIF
INTCON.RXIE
SLPIF
SLPIE
MRF24J40
Bit 7
read.
r
Therefore,
WAKEIF HSYMTMRIF
WAKEIE HSYMTMRIE
Bit 6
INTERRUPT LOGIC
r
the
Bit 5
r
host
Preliminary
SLPCON0.INTEDGE
SECIF
SECIE
Bit 4
r
interrupt until the INTSTAT register is read. The edge
polarity of the INT pin is configured via the INTEDGE
bit in the SLPCON0 (0x211<1>) register.
Note 1: The INTEDGE polarity defaults to:
RXIF
RXIE
Bit 3
2: The INT pin will remain high or low,
r
0 = Falling Edge. Ensure that the inter-
rupt polarity matches the interrupt pin
polarity of the host microcontroller.
depending on INTEDGE polarity setting,
until INTSTAT register is read.
TXG2IE
TXG2IF
Bit 2
r
MRF24J40
INTEDGE
TXG1IE
TXG1IF
Bit 1
DS39776C-page 91
INT
SLPCKEN
TXNIE
TXNIF
Bit 0